sureCore, the ultra-low power embedded IP specialist
Analogue/Mixed Signal Design
The Analogue/Mixed-Signal Design Service has a strong emphasis on low-power design to meet the demands of modern, energy-efficient applications. The sureCore team specialise in creating power-optimised solutions for a wide range of products, including IoT, Edge-AI, wearable and medical devices, as well as sensor interfaces - where minimising energy consumption is critical. Low voltage design has become the defacto solution to address power concerns necessitating in depth marginality analysis. Expertise spans low-power data converters (ADCs/DACs), phase-locked loops (PLLs), bandgaps and DC to DC converters.
With extensive experience designing across a broad range of process nodes—from mature technologies at 180nm down to cutting-edge nodes at 4nm—we offer tailored solutions optimised for each technology generation. Our deep understanding of process-specific design challenges, such as variability in advanced nodes as well as leakage reduction, enables us to deliver highly efficient designs suited to the unique demands of each node. We leverage the strengths of mature nodes (e.g., 180nm, 130nm, and 65nm) for cost-sensitive and analog-centric applications while utilising advanced nodes (e.g., 28nm, 16nm, 7nm, and 4nm) for power-sensitive and high-integration designs.
Our experience spans multiple leading foundries, including TSMC, GlobalFoundries, and Samsung, allowing us to help customers navigate different process technologies, design kits, and PDKs. This multi-foundry expertise enables us to optimise designs for process portability, yield, and cost-efficiency while maintaining consistent performance and reliability. Additionally, we have deep expertise in Fully Depleted Silicon-on-Insulator (FD-SOI) technology, which is ideal for ultra-low-power and low-voltage applications. Leveraging the inherent advantages of FD-SOI, such as reduced leakage current and improved body-biasing capabilities, we develop designs that achieve exceptional power efficiency and performance at lower operating voltages, making FD-SOI an optimal choice for IoT, automotive, and wearable applications.
Our engineers leverage sophisticated simulation, statistical analysis, and verification methodologies to achieve optimal signal integrity, low noise, and efficient power management under varying operating conditions.
With deep experience across process nodes down to 4nm, we address the unique power challenges of advanced technologies, such as leakage current reduction, thermal management, and ultra-low-voltage operation. Our end-to-end services cover every phase of the design lifecycle—from architecture and schematic development to layout, low-power verification, and post-silicon validation—ensuring our customers meet their performance and power targets without compromising reliability.
By prioritising power efficiency at every design stage and leveraging our expertise across multiple foundries and FD-SOI technology, we help customers bring cutting-edge mixed-signal solutions to market that are optimised for low power, enabling longer battery life, reduced heat dissipation, and sustainable, energy-efficient products across a broad spectrum of industries and applications.
Full Custom Transistor Level Layout
The Full Custom Transistor-Level Layout Service provides highly optimised, performance-driven layout solutions tailored to meet the most demanding design specifications. With deep expertise in analogue, digital and mixed-signal design, sureCore delivers fully customised layouts that maximise area efficiency, minimise parasitic effects, and achieve superior power and performance metrics. The team has extensive experience in designing sensitive analogue blocks, such as amplifiers, data converters (ADCs/DACs), PLLs and power management circuits, where precise device matching, symmetry and shielding are critical.
Our layouts are meticulously crafted with advanced techniques, including common-centroid structures, interdigitated device arrays, and carefully balanced routing, ensuring excellent matching and reducing variability. We apply comprehensive Design for Manufacturability (DFM) practices to enhance yield and reliability, incorporating techniques such as dummy device insertion, guard rings, and well proximity effect (WPE) mitigation.
With experience across process nodes from **180nm to 4nm**, including **FD-SOI** and **FinFET technologies**, we are skilled in addressing the challenges of advanced nodes, such as minimising leakage currents, managing variability, and optimising for low power. Additionally, our proficiency in working with multiple foundries, including TSMC, GlobalFoundries and Samsung ensures that our layouts are compliant with foundry-specific design rules and process design kits (PDKs).
We integrate comprehensive post-layout simulations, including parasitic extraction (PEX) and layout-versus-schematic (LVS) verification, to ensure first-pass silicon success. Our commitment to low-power design is reflected in every aspect of the layout, from device-level optimisations to power grid design and electromigration (EM) analysis.
By combining precision craftsmanship with advanced design techniques, our full custom transistor-level layouts deliver superior performance, power efficiency, and reliability—empowering our customers to achieve their design goals and accelerate time-to-market.
Mixed Signal Verification & Characterisation
The Mixed-Signal Verification and Characterisation Service ensures the functionality, performance and robustness of complex analogue-digital designs, accelerating time-to-market with high confidence in silicon success. Statistical analysis is undertaken to ensure design robustness across process, voltage and temperature extremes. In addition, timing analysis and automated liberty file generation can be undertaken where appropriate, facilitating ease of integration.
Our pre-silicon verification employs advanced simulation techniques, including AMS (Analogue Mixed-Signal) simulation, behavioural modelling using Verilog-AMS, Our verification strategy also includes comprehensive checks such as functional verification, noise analysis, and jitter simulations to ensure the design meets performance and power specifications under all operating conditions.
Post-silicon, we conduct thorough characterisation and validation across process, voltage, and temperature (PVT) corners, ensuring the design meets the required specifications in real-world conditions. Our characterisation process includes measuring critical parameters such as gain, offset, linearity (INL/DNL), phase noise, and power consumption. We use custom-designed test setups, automated test equipment (Labview), and lab instrumentation** to ensure accurate measurements and efficient data collection.
By integrating pre-silicon verification with rigorous post-silicon characterisation, we provide a comprehensive solution that reduces risk, shortens debug cycles, and ensures high-performance, low-power mixed-signal designs are production-ready with first-pass success.
Test Chip Development & Evaluation
The Test Chip Development and Evaluation Service enables customers to validate new designs and IP blocks through comprehensive silicon prototyping. End-to-end support, from architecture definition to tape-out and post-silicon evaluation, ensures that critical design parameters are thoroughly tested before full-scale production. Expertise spans custom analogue, digital and mixed-signal IP blocks, including ADCs, DACs, PLLs, SerDes and power management circuits.
We develop multi-project wafer (MPW) test chips, enabling cost-effective prototyping and efficient reuse of wafer space for multiple IPs. Our design-for-test (DFT) methodologies include on-chip test structures, scan chains, and built-in self-test (BIST) circuits to facilitate thorough functional and parametric testing. Additionally, we incorporate process monitors (e.g., ring oscillators and voltage/current references) to characterise the process technology across PVT (process, voltage, temperature) corners.
With extensive experience designing on process nodes from 180nm down to 4nm, including FD-SOI and FinFET technologies, we address advanced-node challenges such as variability, leakage, and electromigration (EM). Our multi-foundry experience with TSMC, GlobalFoundries, and Samsung ensures smooth integration with foundry-specific tape-out and test flows.
Post-silicon, we manage the test chip bring-up, characterisation, and data analysis, using automated test equipment (Labview) and custom lab setups to gather performance metrics such as linearity (INL/DNL), jitter, power efficiency, and timing margins. We analyse results to correlate pre-silicon simulations with measured silicon performance, providing valuable feedback for IP refinement and process optimisation.
Through our comprehensive test chip development services, customers gain early silicon insights, reduce risk, and accelerate their path to first-pass silicon success for production designs.